This invention relates to an output buffer circuit, more particularly to an output buffer circuit with a simple circuit configuration and reduced switching noise.
Switching noise occurring on power supply and ground lines when an output buffer is switched between different states is a serious problem ill integrated circuits. The major cause of such noise is the abrupt charging or discharging of a capacitive output load to which the buffer is connected. A minor cause is direct flow of current from the power supply to ground through the buffer circuit at the instant of switching.
Prior-art solutions to this problem have not been entirely satisfactory. For example, Japanese Patent Application Kokai Publication No. 216518/1986 discloses a tri-state output buffer circuit with two field-effect output transistors, the gates of which are interconnected through a transmission gate that is switched on and off by a control signal. The transmission gate reduces switching noise by delaying the turn-on times of the output transistors, so that they are never both on simultaneously. This scheme eliminates the minor cause of the switching noise problem, but fails to address the major cause.
Reducing the dimensions of the transistors in the transmission gate so that the output transistors turn on more slowly is not a satisfactory solution. Aside from slowing the operation of the circuit, it solves the problem only up to a certain output load capacitance. For larger capacitive loads the problem of switching noise still remains, because the relevant output transistor still turns too quickly in relation to the Charge or discharge time of the capacitive output load.
Japanese Patent Application Kokai Publication No. 244124/1986 discloses an output buffer circuit having two or more pull-up output transistors coupled in parallel to the power supply, and two or more pull-down output transistors coupled in parallel to ground. The turn-on times of the transistors are staggered so as to reduce peak charge or discharge current, while providing sufficient current-driving ability after all pull-up or pull-down transistors have been turned on. The drawback of this scheme is the large number of circuit elements required, e.g. twenty-four transistors in the disclosed circuit, many having their drains connected directly to the output terminal and requiring large pattern areas to prevent such problems as latch-up. This scheme is accordingly inappropriate for gate arrays and other devices in which a large number of output buffers must fit into a restricted space.